Right, that is indeed happening, but it appears to be very simple in the chip, something like CLKO = VCC - CLKI. The signal retains its “shape”, even though it’s inverted.
I can see how that statement could be misunderstood to imply it’s reshaping the signal (so that it’s a nice square wave), but it does not appear to be doing this like it does with the data line.
I doubt that this will reveal any other revelation than what’s already been discovered, but Julian Ilett did two videos on the APA102s where he talks about the clock signal and bits being sent and what not:
Part 1: https://www.youtube.com/watch?v=UYvC-hukz-0
Part 2: https://www.youtube.com/watch?v=i4qh1HFU9-s
@Gabriel_Schine
Did I say the clock line was reshaped? (hint: no)
The data is reshaped, and since the data is by definition only valid during the rising edge of the clock signal, the moment in which it is received is delayed by T(CLK-ON), which I rather imprecisely expressed as “half a clock cycle”.
@Luminous_Elements my apologies. I thought you might have misinterpreted it.
There doesn’t appear to be any disagreement at all, then.