A recent article on PJRC details how some APA102s can distort the clock signal at high data rates and cause the clock duty cycle to creep towards more time high. This eventually messes up the clock/data timing and makes it hard to have long strips at high data rates.
If there was a way to adjust the clock duty cycle to more time low, before it even got into the LEDs, that could help increase strip length. Maybe a level shifter that reduces the clock signal voltage to just above the spec 0.7*VDD so it only registers as high for a narrow width of the clock high, assuming the clock signal is getting less square. Could also do this at regular intervals along the LEDs to correct the clock.