After realizing that the Teensy 3.1 and FastLed 3.1 are able to support 16 channels of Leds I whipped up this quick breakout board using octal buffered 5V outputs just like the Fadecandy. With the Chinese New Year upon us, I’ll be sending these off to Oshpark for fab.
Based on recent efforts were are coordinating the port of LEDscape to support APA102 over parallel channels of data. I am curious if FastLed 3.1 would be able to support the APA102 in SPI mode using the DMA and a single shared clock pin that could be shared over 8 ports. We can do this with the BBB and assume we could as well with the Freescale chipset?
It’s something I’m planning on doing, unclear whether it’d be worth it to do DMA or not. (It may not be, because of the CPU time required to rotate bits/bytes - I may as well drive the SPI data out interleaved with the bit rotations).
Of course, the problem with parallel output for APA102 is this. APA102, right now, I can push at 24Mbps. That’s ~22 times faster (accounting for the 32 bit package vs. 24 bit package) than the WS2812.
Part of how I can parallel output the 2812 efficiently on the teensy 3 is that it takes me 77 clocks to do each of the two sets of 8x8 bit rotations that I need to do to prep the data for parallel output. This happens in under 1µs, which means I can slip it into the space between individual bytes. However, because of the cost of the bit rotation, that tells me that I will be getting, at best, ~1Mbps out over each line if I were to run them in parallel. So, if I could do 16-way parallel APA106, the overhead of doing the bit/byte rotation would be high enough that it would potentially be slower than just pushing APA102’s at their full 24Mbps data rate.
Of course, on the BBB you have far more CPU cycles that you can use to pre-rotate the bit data before handing it off to the PRU to write it out in parallel, so you’d probably be able to get a fair bit further along.
(Everyone forgets about the cost of that bit/byte rotation - if you aren’t handing it pre-rotated data, OctoWS2811’s overhead for it’s bit/byte rotation makes it slower than FastLED3.1’s parallel output, completely negating the advantage of driving it via DMA)
Daniel, thanks for all the consideration. I definitely realize that by paralleling the output for APA102 (SPI) it may indeed be slower (1Mbps). You bring up a good point that it may indeed be easier to just link them serially at (24 MBps). I never really thought about it that way.
Obviously parallel outputs can be beneficial from a reliability standpoint due to the reduced number leds in a chain that can fail.
But in that case what you do is run them in multiple strips and just rotate a 24mbps SPI output amongst them :). One thing I like on the nrf51822 is that I can put “SPI” on any pair of pins I want to. I wish I could do that on other chipsets.
Rotating the pins to SPI would be awesome. I have a ghetto version of the board with that uses one of the BBB capes of similar design. HAving the level shifters makes things alot more robust and eliminates alot of noise. I have the initial board off to OSHPARK (3) otherwise I’d have more boards if it wasn’t for the Chinese New Year. I’ll definitely drop one of them in the post to you.
